Invention Grant
- Patent Title: Bumpless build-up layer and laminated core hybrid structures and methods of assembling same
- Patent Title (中): 无皱堆积层和层叠芯混合结构及其组装方法
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Application No.: US13934522Application Date: 2013-07-03
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Publication No.: US08809124B2Publication Date: 2014-08-19
- Inventor: Mathew J Manusharow , Mark S Hlad , Ravi K Nalla
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Winkle, PLLC
- Main IPC: H01L23/485
- IPC: H01L23/485
Abstract:
A structure includes a hybrid substrate for supporting a semiconductive device that includes a bumpless build-up layer in which the semiconductive device is embedded and a laminated-core structure. The bumpless build-up layer and the laminated-core structure are rendered an integral apparatus by a reinforcement plating that connects to a plated through hole in the laminated-core structure and to a subsequent bond pad of the bumpless build-up layer structure.
Public/Granted literature
- US20130344662A1 BUMPLESS BUILD-UP LAYER AND LAMINATED CORE HYBRID STRUCTURES AND METHODS OF ASSEMBLING SAME Public/Granted day:2013-12-26
Information query
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