发明授权
US08791844B2 Modified dynamic element matching for reduced latency in a pipeline analog to digital converter
有权
改进的动态元素匹配,以减少流水线模数转换器的延迟
- 专利标题: Modified dynamic element matching for reduced latency in a pipeline analog to digital converter
- 专利标题(中): 改进的动态元素匹配,以减少流水线模数转换器的延迟
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申请号: US13489865申请日: 2012-06-06
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公开(公告)号: US08791844B2公开(公告)日: 2014-07-29
- 发明人: Daniel Meacham , Andrea Panigada , Jorge Grilo
- 申请人: Daniel Meacham , Andrea Panigada , Jorge Grilo
- 申请人地址: US AZ Chandler
- 专利权人: Microchip Technology Incorporated
- 当前专利权人: Microchip Technology Incorporated
- 当前专利权人地址: US AZ Chandler
- 代理机构: King & Spalding L.L.P.
- 主分类号: H03M1/06
- IPC分类号: H03M1/06
摘要:
A circuit in an analog-to-digital converter (ADC) includes an amplifier configured to receive an output of a backend DAC; a harmonic distortion correction circuit (HDC) coupled to the amplifier and configured to correct distortion components due to the residue amplifier present in a digital signal from the backend ADC, the HDC circuit providing an output to an adder, the adder receiving a coarse digital output from a coarse ADC; and a DAC noise cancellation circuit (DNC) configured to provide an output to the adder, wherein the DNC circuit is configured to correct distortion components due to the DAC present in the digital signal from the backend ADC; wherein the output of the adder is an ADC digital output and wherein the ADC digital output forms an input to the HDC and the DNC.
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