发明授权
US08785979B2 Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with two inside positioned gate contacts and two outside positioned gate contacts and electrical connection of cross-coupled transistors through same interconnect layer
有权
集成电路包括交叉耦合晶体管，其具有形成在门级特征布局通道内的栅电极，其具有两个内部定位的栅极触点和两个外部定位的栅极触点以及通过相互互连层的交叉耦合晶体管的电连接
- 专利标题： Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with two inside positioned gate contacts and two outside positioned gate contacts and electrical connection of cross-coupled transistors through same interconnect layer
- 专利标题（中）： 集成电路包括交叉耦合晶体管，其具有形成在门级特征布局通道内的栅电极，其具有两个内部定位的栅极触点和两个外部定位的栅极触点以及通过相互互连层的交叉耦合晶体管的电连接
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申请号： US12753776申请日： 2010-04-02
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公开(公告)号： US08785979B2公开(公告)日： 2014-07-22
- 发明人: Scott T. Becker , Jim Mali , Carole Lambert
- 申请人： Scott T. Becker , Jim Mali , Carole Lambert
- 申请人地址： US CA Los Gatos
- 专利权人： Tela Innovations, Inc.
- 当前专利权人： Tela Innovations, Inc.
- 当前专利权人地址： US CA Los Gatos
- 代理机构： Martine Penilla Group, LLP
- 主分类号： H01L27/10
- IPC分类号： H01L27/10
摘要：
A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature, with a centerline of each originating rectangular-shaped layout feature aligned in a parallel manner. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. Widths of the first and second p-type diffusion regions are different, such that the first and second PMOS transistor devices have different widths. Widths of the first and second n-type diffusion regions are different, such that the first and second NMOS transistor devices have different widths. The first and second PMOS and first and second NMOS transistor devices form a cross-coupled transistor configuration.
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