发明授权
- 专利标题: Method of forming an interconnect structure having an enlarged region
- 专利标题(中): 形成具有扩大区域的互连结构的方法
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申请号: US13953418申请日: 2013-07-29
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公开(公告)号: US08785323B2公开(公告)日: 2014-07-22
- 发明人: Chien-Jung Wang
- 申请人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Slater and Matsil, L.L.P.
- 主分类号: H01L21/4763
- IPC分类号: H01L21/4763
摘要:
A method of forming an interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via.
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