发明授权
- 专利标题: Writing method of nonvolatile semiconductor memory device
- 专利标题(中): 非易失性半导体存储器件的写入方法
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申请号: US13760737申请日: 2013-02-06
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公开(公告)号: US08755228B2公开(公告)日: 2014-06-17
- 发明人: Akio Kaneko , Wataru Sakamoto
- 申请人: Kabushiki Kaisha Toshiba
- 申请人地址: JP Minato-ku
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JP Minato-ku
- 代理机构: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- 主分类号: G11C16/04
- IPC分类号: G11C16/04
摘要:
According to one embodiment, there is provided a writing method. The method includes setting potentials of a plurality of word lines to a first potential. The first potential is a potential to allow memory cells corresponding to a selective bit line to be in on state. The method also includes setting potentials of non-adjacent word lines to a second potential while maintaining potentials of adjacent word lines at a potential which allows the memory cells corresponding to the selective bit line to be in on state and setting a potential of a selective word line to a third potential. The second potential is a potential which is determined so as to allow the memory cells corresponding to the selective bit line to be in off state. The third potential is a potential where data is written in the selective memory cell corresponding to the selective bit line.
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