发明授权
- 专利标题： Via-configurable high-performance logic block architecture
- 专利标题（中）： 通过可配置的高性能逻辑块架构
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申请号： US13271679申请日： 2011-10-12
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公开(公告)号： US08735857B2公开(公告)日： 2014-05-27
- 发明人: Alexander Andreev , Sergey Gribok , Ranko Scepanovic
- 申请人： Alexander Andreev , Sergey Gribok , Ranko Scepanovic
- 申请人地址： US CA Santa Clara
- 专利权人： eASIC Corporation
- 当前专利权人： eASIC Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Novak Druce Connolly Bove + Quigg LLP
- 主分类号： H01L27/08
- IPC分类号： H01L27/08 ; H01L47/00
摘要：
A via-configurable circuit block may contain chains of p-type and n-type transistors that may or may not be interconnected by means of configurable vias. Configurable vias may also be used to connect various transistor terminals to a ground line, a power line and/or to various terminals that may provide connections outside of the circuit block.
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