Invention Grant
US08732548B2 Instruction-set architecture for programmable cyclic redundancy check (CRC) computations
有权
用于可编程循环冗余校验（CRC）计算的指令集架构
- Patent Title: Instruction-set architecture for programmable cyclic redundancy check (CRC) computations
- Patent Title (中): 用于可编程循环冗余校验（CRC）计算的指令集架构
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Application No.: US13793358Application Date: 2013-03-11
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Publication No.: US08732548B2Publication Date: 2014-05-20
- Inventor: Vinodh Gopal , Shay Gueron , Gilbert Wolrich , Wajdi Feghali , Kirk Yap , Bradley Burres
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: H03M13/00
- IPC: H03M13/00
Abstract:
A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands.
Public/Granted literature
- US20130191699A1 INSTRUCTION-SET ARCHITECTURE FOR PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) COMPUTATIONS Public/Granted day:2013-07-25
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