发明授权
US08687436B2 Increasing efficiency of memory accesses by selectively introducing a relative delay between the time that write addresses are provided to the memory and the time that write data is provided to the memory
失效
通过在写入地址被提供给存储器的时间和向存储器提供写入数据的时间之间选择性地引入相对延迟来提高存储器访问的效率
- 专利标题： Increasing efficiency of memory accesses by selectively introducing a relative delay between the time that write addresses are provided to the memory and the time that write data is provided to the memory
- 专利标题（中）： 通过在写入地址被提供给存储器的时间和向存储器提供写入数据的时间之间选择性地引入相对延迟来提高存储器访问的效率
-
申请号： US13442382申请日： 2012-04-09
-
公开(公告)号： US08687436B2公开(公告)日： 2014-04-01
- 发明人: J. Thomas Pawlowski
- 申请人： J. Thomas Pawlowski
- 申请人地址： US NJ Jersey City
- 专利权人： Round Rock Research, LLC
- 当前专利权人： Round Rock Research, LLC
- 当前专利权人地址： US NJ Jersey City
- 代理机构： Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- 主分类号： G06F12/00
- IPC分类号： G06F12/00
摘要：
Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access.
公开/授权文献
- US20120198194A1 Multi-Bank Memory Accesses Using Posted Writes 公开/授权日：2012-08-02
信息查询
