There is provided an image/video processor comprises an embedded memory for image/video data that including a plurality of unit memory blocks including a plurality of memory cells; and a controller configured to store each bit of image/video data received through an input/output unit in each memory cell, read the image/video data stored in each memory cell of the embedded memory, and output the image/video data through the input/output unit, wherein at least two or more memory cells included in the plurality of memory cells have different sizes, the controller assign each bit of the image/video data depending on the importance of the image/video data and a size of the memory cell, and as the size of the memory cell is larger, a bit of image/video data of high importance is assigned.