发明授权
US08601427B2 Intergrated circuit having latch circuits and using delay to fetch data bits in synchronization with clock signals
有权
集成电路具有锁存电路并且使用延迟来与时钟信号同步地获取数据位
- 专利标题： Intergrated circuit having latch circuits and using delay to fetch data bits in synchronization with clock signals
- 专利标题（中）： 集成电路具有锁存电路并且使用延迟来与时钟信号同步地获取数据位
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申请号： US13362414申请日： 2012-01-31
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公开(公告)号： US08601427B2公开(公告)日： 2013-12-03
- 发明人: Masakuni Kawagoe
- 申请人： Masakuni Kawagoe
- 申请人地址： JP Tokyo
- 专利权人： Lapis Semiconductor Co., Ltd.
- 当前专利权人： Lapis Semiconductor Co., Ltd.
- 当前专利权人地址： JP Tokyo
- 代理机构： Volentine & Whitt, PLLC.
- 优先权： JP2011-025807 20110209
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A semiconductor integrated circuit includes a delay circuit connected between a source of data bits and a data input terminal of a latch circuit. The delay circuit includes a first delay section formed by connecting logic devices in series corresponding to a number of logic devices included in a clock signal path between a clock signal source and the latch circuit data input. The delay circuit also includes a second delay section having a delay time equal to an interconnect delay time corresponding to a wiring length of the clock signal path.
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