发明授权
- 专利标题： Voltage generation circuit which is capable of reducing circuit area
- 专利标题（中）： 能够减少电路面积的电压产生电路
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申请号： US13239948申请日： 2011-09-22
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公开(公告)号： US08593874B2公开(公告)日： 2013-11-26
- 发明人: Tatsuro Midorikawa
- 申请人： Tatsuro Midorikawa
- 申请人地址： JP Tokyo
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JP Tokyo
- 代理机构： Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- 优先权： JP2010-245284 20101101
- 主分类号： G11C11/34
- IPC分类号： G11C11/34 ; G11C16/04 ; G11C5/14
摘要：
According to one embodiment, a voltage generation circuit includes a first boost circuit, a first output circuit, a rectifying circuit, a second output circuit, and a detection circuit. The first boost circuit outputs a first voltage in first and second operation modes. The first output circuit is connected to the first boost circuit, and outputs the first voltage as a second voltage in the first operation mode. The rectifying circuit is connected to the first boost circuit, and outputs a third voltage which is lower than the first voltage in the first operation mode. The second output circuit short-circuits the rectifying circuit in the second operation mode, and outputs the first voltage as a fourth voltage. The detection circuit detects the second and fourth voltages which are supplied from the first and second output circuits.
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