Invention Grant
US08524561B2 Methods of forming a plurality of transistor gates, and methods of forming a plurality of transistor gates having at least two different work functions
有权
形成多个晶体管栅极的方法,以及形成具有至少两个不同功函数的多个晶体管栅极的方法
- Patent Title: Methods of forming a plurality of transistor gates, and methods of forming a plurality of transistor gates having at least two different work functions
- Patent Title (中): 形成多个晶体管栅极的方法,以及形成具有至少两个不同功函数的多个晶体管栅极的方法
-
Application No.: US13248625Application Date: 2011-09-29
-
Publication No.: US08524561B2Publication Date: 2013-09-03
- Inventor: Gurtej S. Sandhu , Mark Kiehlbauch
- Applicant: Gurtej S. Sandhu , Mark Kiehlbauch
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John, P.S.
- Main IPC: H01L21/8234
- IPC: H01L21/8234

Abstract:
A method of forming a plurality of transistor gates having at least two different work functions includes forming first and second transistor gates over a substrate having different widths, with the first width being narrower than the second width. A material is deposited over the substrate including over the first and second gates. Within an etch chamber, the material is etched from over both the first and second gates to expose conductive material of the first gate and to reduce thickness of the material received over the second gate yet leave the second gate covered by the material. In situ within the etch chamber after the etching, the substrate is subjected to a plasma comprising a metal at a substrate temperature of at least 300° C. to diffuse said metal into the first gate to modify work function of the first gate as compared to work function of the second gate.
Public/Granted literature
Information query
IPC分类: