Invention Grant
US08488357B2 Reference cell architectures for small memory array block activation
有权
小型存储器阵列块激活的参考单元结构
- Patent Title: Reference cell architectures for small memory array block activation
- Patent Title (中): 小型存储器阵列块激活的参考单元结构
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Application No.: US12925492Application Date: 2010-10-22
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Publication No.: US08488357B2Publication Date: 2013-07-16
- Inventor: Toshio Sunaga , Lejan Pu , Perng-Fei Yuh , Chao-Hung Chang
- Applicant: Toshio Sunaga , Lejan Pu , Perng-Fei Yuh , Chao-Hung Chang
- Applicant Address: US CA Milpitas
- Assignee: MagIC Technologies, Inc.
- Current Assignee: MagIC Technologies, Inc.
- Current Assignee Address: US CA Milpitas
- Agency: Saile Ackerman LLC
- Agent Stephen B. Ackerman
- Main IPC: G11C5/08
- IPC: G11C5/08

Abstract:
Systems and methods for realizing reference currents to improve reliability of sensing operations of segmented semiconductor memory arrays have been achieved. Preferred embodiments of the invention comprise MRAM arrays but the invention could be applied to any other memories requiring access on small, segmented arrays. All embodiments of the invention comprise a folded bit lines scheme, either in adjacent bit lines or in segment-to-segment folded bit lines. In two embodiments alternate strapping of Poly-Si Word Lines in every second segment is achieved by metal layer of Read Word Line and Write Select Line. An embodiment has stored 1 and 0 cells on both sides of a selected segment to be read.
Public/Granted literature
- US20120099358A1 Reference cell architectures for small memory array block activation Public/Granted day:2012-04-26
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