Invention Grant
US08433944B2 Clock divider system and method with incremental adjustment steps while controlling tolerance in clock duty cycle 失效
时钟分频器系统和方法具有增量调节步骤,同时控制时钟占空比的容限

Clock divider system and method with incremental adjustment steps while controlling tolerance in clock duty cycle
Abstract:
In a particular embodiment, a single step increment calculation module is responsive to a first ramp control value and a second ramp control value. The single step increment calculation module generates a single step frequency adjustment as an output. The generated single step frequency adjustment is applied to a system clock signal having a first frequency to change the system clock signal to a second clock signal having a second frequency. The first frequency is different from the second frequency and the system clock signal has a first duty cycle that is within a tolerance range of a second duty cycle of the second clock signal.
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