Invention Grant
US08433944B2 Clock divider system and method with incremental adjustment steps while controlling tolerance in clock duty cycle
失效
时钟分频器系统和方法具有增量调节步骤，同时控制时钟占空比的容限
- Patent Title: Clock divider system and method with incremental adjustment steps while controlling tolerance in clock duty cycle
- Patent Title (中): 时钟分频器系统和方法具有增量调节步骤，同时控制时钟占空比的容限
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Application No.: US12758374Application Date: 2010-04-12
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Publication No.: US08433944B2Publication Date: 2013-04-30
- Inventor: Srinjoy Das , Haikun Zhu , Kevin R. Bowles , Matthew L. Severson
- Applicant: Srinjoy Das , Haikun Zhu , Kevin R. Bowles , Matthew L. Severson
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Nicholas J. Pauley; Peter Michael Kamarchik; Joseph Agusta
- Main IPC: G06F1/00
- IPC: G06F1/00
Abstract:
In a particular embodiment, a single step increment calculation module is responsive to a first ramp control value and a second ramp control value. The single step increment calculation module generates a single step frequency adjustment as an output. The generated single step frequency adjustment is applied to a system clock signal having a first frequency to change the system clock signal to a second clock signal having a second frequency. The first frequency is different from the second frequency and the system clock signal has a first duty cycle that is within a tolerance range of a second duty cycle of the second clock signal.
Public/Granted literature
- US20110248764A1 Clock Divider System and Method Public/Granted day:2011-10-13
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