发明授权
- 专利标题: Multi level inhibit scheme
- 专利标题(中): 多级抑制方案
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申请号: US12981688申请日: 2010-12-30
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公开(公告)号: US08422297B2公开(公告)日: 2013-04-16
- 发明人: Satoru Tamada
- 申请人: Satoru Tamada
- 申请人地址: US ID Boise
- 专利权人: Micron Technology, Inc.
- 当前专利权人: Micron Technology, Inc.
- 当前专利权人地址: US ID Boise
- 代理机构: Leffert Jay & Polglaze, P.A.
- 优先权: JP2008-034423 20080215
- 主分类号: G11C16/04
- IPC分类号: G11C16/04 ; G11C11/40
摘要:
Memory devices and methods are disclosed to facilitate utilization of a multi level inhibit programming scheme. In one such embodiment, isolated channel regions having boosted channel bias levels are formed across multiple memory cells and are created in part and maintained through capacitive coupling with word lines coupled to the memory cells and biased to predetermined bias levels. Methods of manipulation of isolated channel region bias levels through applied word line bias voltages affecting a program inhibit effect, for example, are also disclosed.
公开/授权文献
- US20110096599A1 MULTI LEVEL INHIBIT SCHEME 公开/授权日:2011-04-28
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