The present invention relates to an information processing apparatus capable of accurately controlling DMA transfer of a plurality of pieces of data present in a memory with a simple hardware configuration, and an information processing method for use therewith. A memory 33 is provided with a descriptor table T0 corresponding to a queue Q0 and a descriptor table T1 corresponding to a queue Q1. In registers R0 and R1 of a descriptor controller 51, the descriptor number constituting the descriptor table T0 and the descriptor number constituting the descriptor table T1 are recorded, respectively. In caches C0 and C1 of a descriptor obtaining section 52, descriptors of the descriptor table T0 and descriptors of the descriptor table T1 are recorded, respectively. A descriptor selector 53 selects one of the caches C0 and C1 in accordance with a predetermined rule. The present invention can be applied to all electronic apparatuses for performing DMA transfer.