A solid state power controller (SSPC) for a direct current (DC) electrical system includes a high bandwidth fault detector, the high bandwidth fault detector configured to detect a possible fault and place a power switch of the SSPC in saturation at a predetermined current limit; and a low bandwidth fault detector, the low bandwidth fault detector configured to determine whether the possible fault is a confirmed fault, and in the event the possible fault is determined to be the confirmed fault, turning off the power switch, or in the event the possible fault is determined not to be the confirmed fault, turning on the power switch at a minimum on-resistance.