发明授权
- 专利标题： Bias circuit with high enablement speed and low leakage current
- 专利标题（中）： 偏置电路具有高启动速度和低漏电流
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申请号： US12945543申请日： 2010-11-12
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公开(公告)号： US08384471B2公开(公告)日： 2013-02-26
- 发明人: Hung-Chang Yu
- 申请人： Hung-Chang Yu
- 申请人地址： TW Hsin-Chu
- 专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址： TW Hsin-Chu
- 代理机构： Slater & Matsil, L.L.P.
- 主分类号： G05F3/26
- IPC分类号： G05F3/26 ; G05F3/24
摘要：
A circuit includes a first PMOS transistor and a second PMOS transistor, wherein a gate of the second PMOS transistor is coupled to a gate and a drain of the first PMOS transistor; a first NMOS transistor having a drain coupled to a drain of the first PMOS transistor; and a second NMOS transistor, wherein a drain of the second NMOS transistor is coupled to a gate of the first NMOS transistor, a gate of the second NMOS transistor, and a drain of the second PMOS transistor. A first switch is coupled between the drain of the first PMOS transistor and the drain of the second PMOS transistor. A second switch is coupled between a source of the first NMOS transistor and an electrical ground. A third switch is coupled between a source of the second NMOS transistor and the electrical ground.
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