The application discloses a circuit comprising at least one flip flop, said flip flop comprising: a master latch and a slave latch; a data signal input and a scan signal input arranged in parallel to each other and each input comprising a tristateable device; and a scan enable signal input, a functional clock signal input and a scan clock signal input; wherein: in response to a first predetermined value of said scan enable signal indicating a functional mode of operation, said scan input tristateable device is operable to isolate said scan input from said master latch, and said master latch is operable in response to said functional clock to receive data from said data input and to output data to said slave latch and said slave latch is operable in response to said functional clock to receive data from said master latch and to output data at said data output; and in response to a second predetermined value of said scan enable signal indicating a scan mode of operation said data input tristateable device is operable to isolate said data input from said master latch, and said master latch is operable in response to said scan clock to receive data from said scan input and said slave latch is operable in response to said functional clock to receive data from said master latch and to output data at said scan output.