发明授权
- 专利标题: Modeling electrical interconnections in three-dimensional structures
- 专利标题(中): 在三维结构中建模电互连
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申请号: US12288616申请日: 2008-10-22
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公开(公告)号: US08352232B2公开(公告)日: 2013-01-08
- 发明人: Ki Jin Han , Madhavan Swaminathan
- 申请人: Ki Jin Han , Madhavan Swaminathan
- 申请人地址: US GA Atlanta
- 专利权人: Georgia Tech Research Corporation
- 当前专利权人: Georgia Tech Research Corporation
- 当前专利权人地址: US GA Atlanta
- 代理机构: Bockhop & Associates, LLC
- 代理商 Bryan W. Bockhop
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; G06F9/455
摘要:
Disclosed are apparatus, methods and software that implement a partial element equivalent circuit (PEEC) method having global basis functions on cylindrical coordinates to determine wide-band resistance, inductance, capacitance, and conductance from a large number of three-dimensional interconnections in order to provide for the electrical design of system-in-package (SIP) modules, and the like. The apparatus, methods and software use a modal equivalent network from mixed potential integral equation with cylindrical conduction and accumulation mode basis functions, which reduces the matrix size for large three-dimensional interconnection problems. Combined with these modal basis functions, the mixed potential integral equations describe arbitrary skin and proximity effects, and allow determination of partial impedance and admittance values. Additional enhancement schemes further reduces the cost for computing the partial inductances. Therefore, the apparatus, methods and software can be used to construct accurate models of a large number of three-dimensional interconnection structures, including more than 100 bonding wires used for stacking integrated circuit chips, through-silicon via interconnections, and the like.
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