发明授权
US08341628B2 Controlling depth and latency of exit of a virtual processor's idle state in a power management environment
失效
在电源管理环境中控制虚拟处理器空闲状态退出的深度和延迟
- 专利标题： Controlling depth and latency of exit of a virtual processor's idle state in a power management environment
- 专利标题（中）： 在电源管理环境中控制虚拟处理器空闲状态退出的深度和延迟
-
申请号： US12645597申请日： 2009-12-23
-
公开(公告)号： US08341628B2公开(公告)日： 2012-12-25
- 发明人: Richard Louis Arndt , Christopher Francois , Naresh Nayar , Karthick Rajamani , Freeman Leigh Rawson, III , Randal Craig Swanberg
- 申请人： Richard Louis Arndt , Christopher Francois , Naresh Nayar , Karthick Rajamani , Freeman Leigh Rawson, III , Randal Craig Swanberg
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 代理机构： Yudell Isidore Ng Russell PLLC
- 主分类号： G06F9/455
- IPC分类号： G06F9/455 ; G06F1/00
摘要：
A mechanism is provided in a logically partitioned data processing system for controlling depth and latency of exit of a virtual processor's idle state. A virtualization layer generates a cede latency setting information (CLSI) data. Responsive to booting a logical partition, the virtualization layer communicates the CLSI data to an operating system (OS) of the logical partition. The OS determines, based on the CLSI data, a particular idle state of a virtual processor under a control of the OS. Responsive to the OS calling the virtualization layer, the OS communicates the particular idle state of the virtual processor to the virtualization layer for assigning the particular idle state and wake-up characteristics to the virtual processor.
公开/授权文献
信息查询
