发明授权
US08293587B2 Multilayer pillar for reduced stress interconnect and method of making same
有权
用于减少应力互连的多层支柱及其制造方法
- 专利标题： Multilayer pillar for reduced stress interconnect and method of making same
- 专利标题（中）： 用于减少应力互连的多层支柱及其制造方法
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申请号： US11870583申请日： 2007-10-11
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公开(公告)号： US08293587B2公开(公告)日： 2012-10-23
- 发明人: Virendra R Jadhav , Krystyna W Semkow , Kamalesh K Srivastava , Brian R Sundlof
- 申请人： Virendra R Jadhav , Krystyna W Semkow , Kamalesh K Srivastava , Brian R Sundlof
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 代理机构： Roberts, Mlotkowski, Safran & Cole, P.C.
- 代理商 Joseph Petrokaitis
- 主分类号： H01L21/00
- IPC分类号： H01L21/00
摘要：
A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
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