Invention Grant
- Patent Title: Semiconductor integrated circuit device and method of arranging wirings in the semiconductor integrated circuit device
- Patent Title (中): 半导体集成电路器件以及在半导体集成电路器件中配线的方法
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Application No.: US12426444Application Date: 2009-04-20
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Publication No.: US08284584B2Publication Date: 2012-10-09
- Inventor: Eiichi Makino
- Applicant: Eiichi Makino
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2008-109816 20080421
- Main IPC: G11C5/06
- IPC: G11C5/06

Abstract:
A semiconductor integrated circuit device includes a first component, a second component, a plurality of first, second and third contacts, and a plurality of signal lines having a plurality of first wires, and connecting the first and second component, each of the first wires having a first, second, third and fourth part, each of the parts having a resistivity, the second part having a first resistivity, a different value of the first resistance being set for each of the plurality of first wires, the first, third and fourth parts having a second or third resistivity which is lower than the first resistivity, the first and second part being electrically connected in series by the first contact, the second and third part being electrically connected in series by the second contact, and the third and fourth part being electrically connected in series by the third contact.
Public/Granted literature
Information query