发明授权
US08283262B2 Method for depositing a layer on a semiconductor wafer by means of CVD and chamber for carrying out the method
有权
用于通过CVD和室在半导体晶片上沉积层以执行该方法的方法
- 专利标题: Method for depositing a layer on a semiconductor wafer by means of CVD and chamber for carrying out the method
- 专利标题(中): 用于通过CVD和室在半导体晶片上沉积层以执行该方法的方法
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申请号: US12499924申请日: 2009-07-09
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公开(公告)号: US08283262B2公开(公告)日: 2012-10-09
- 发明人: Georg Brenninger , Alois Aigner
- 申请人: Georg Brenninger , Alois Aigner
- 申请人地址: DE Munich
- 专利权人: Siltronic AG
- 当前专利权人: Siltronic AG
- 当前专利权人地址: DE Munich
- 代理机构: Leydig, Voit & Mayer, Ltd.
- 优先权: DE102008034260 20080716
- 主分类号: H01L21/00
- IPC分类号: H01L21/00
摘要:
A method for depositing a layer on a semiconductor wafer using chemical vapor deposition (CVD). The method includes providing a chamber having an inlet opening and an outlet opening and a channel joining the inlet opening and the outlet opening, wherein the channel is bounded at the bottom by a plane and at the top by a window transmissive to thermal radiation. A semiconductor wafer is disposed so that a surface of the semiconductor lies in the plane, wherein the window has a center region disposed over the semiconductor wafer and an edge region surrounding the center region and not disposed over the semiconductor wafer. A distance between the plane and the window varies across the chamber, the distance being greater at the edge region than at the center region. A tangent applied to a radial profile of the distance at a boundary between the center region and the edge region forms an angle with the plane of not less than 15° and not more than 25°. A deposition gas is conducted through the channel from the gas inlet opening over the semiconductor wafer to the gas outlet opening, wherein a speed at which the deposition gas is conducted varies over the semiconductor wafer according to the varying distance between the plane and the window.
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