发明授权
- 专利标题： Parallel memory device rank selection
- 专利标题（中）： 并行存储设备等级选择
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申请号： US13168455申请日： 2011-06-24
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公开(公告)号： US08275956B2公开(公告)日： 2012-09-25
- 发明人: Lidia Warnes , Teddy Lee , Ricardo Ernesto Espinoza-Ibarra , Dennis Carr , Michael Bozich Calhoun
- 申请人： Lidia Warnes , Teddy Lee , Ricardo Ernesto Espinoza-Ibarra , Dennis Carr , Michael Bozich Calhoun
- 申请人地址： US TX Houston
- 专利权人： Hewlett-Packard Development Company, L.P.
- 当前专利权人： Hewlett-Packard Development Company, L.P.
- 当前专利权人地址： US TX Houston
- 主分类号： G06F12/00
- IPC分类号： G06F12/00 ; G06F13/00 ; G06F13/28
摘要：
A translator circuit translates a memory access conforming to a native FB-DIMM (Fully Buffered Dual In-Line Memory Module) protocol to a memory access for addressing more than two ranks of parallel memory devices. The parallel memory devices are distributed among plural non-fully-buffered DIMMs (Dual In-Line Memory Modules).
公开/授权文献
- US20110258400A1 PARALLEL MEMORY DEVICE RANK SELECTION 公开/授权日：2011-10-20
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