发明授权
- 专利标题： Reduction of edge effects from aspect ratio trapping
- 专利标题（中）： 从纵横比捕获中减少边缘效应
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申请号： US12495161申请日： 2009-06-30
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公开(公告)号： US08274097B2公开(公告)日： 2012-09-25
- 发明人: Zhiyuan Cheng
- 申请人： Zhiyuan Cheng
- 申请人地址： TW Hsin-Chu
- 专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址： TW Hsin-Chu
- 代理机构： Slater & Matsil, L.L.P.
- 主分类号： H01L21/02
- IPC分类号： H01L21/02
摘要：
A device includes a crystalline material within an area confined by an insulator. In one embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique. Method and apparatus embodiments of the invention can reduce edge effects in semiconductor devices. Embodiments of the invention can provide a planar surface over a buffer layer between a plurality of uncoalesced ART structures.
公开/授权文献
- US20100025683A1 REDUCTION OF EDGE EFFECTS FROM ASPECT RATION TRAPPING 公开/授权日：2010-02-04
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