发明授权
US08269523B2 VLSI layouts of fully connected generalized networks 有权
完全连接的广义网络的VLSI布局

  • 专利标题: VLSI layouts of fully connected generalized networks
  • 专利标题(中): 完全连接的广义网络的VLSI布局
  • 申请号: US12601275
    申请日: 2008-05-22
  • 公开(公告)号: US08269523B2
    公开(公告)日: 2012-09-18
  • 发明人: Venkat Konda
  • 申请人: Venkat Konda
  • 申请人地址: US CA San Jose
  • 专利权人: Konda Technologies Inc.
  • 当前专利权人: Konda Technologies Inc.
  • 当前专利权人地址: US CA San Jose
  • 国际申请: PCT/US2008/064605 WO 20080522
  • 国际公布: WO2008/147928 WO 20081204
  • 主分类号: H03K19/177
  • IPC分类号: H03K19/177
VLSI layouts of fully connected generalized networks
摘要:
In accordance with the invention, VLSI layouts of generalized multi-stage networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links. The VLSI layouts employ shuffle exchange links where outlet links of cross links from switches in a stage in one sub-integrated circuit block are connected to inlet links of switches in the succeeding stage in another sub-integrated circuit block so that said cross links are either vertical links or horizontal and vice versa. In one embodiment the sub-integrated circuit blocks are arranged in a hypercube arrangement in a two-dimensional plane. The VLSI layouts exploit the benefits of significantly lower cross points, lower signal latency, lower power and full connectivity with significantly fast compilation.The VLSI layouts presented are applicable to generalized multi-stage networks V(N1, N2, d, s), generalized folded multi-stage networks Vfold(N1, N2, d, s), generalized butterfly fat tree networks Vbft(N1, N2, d, s), generalized multi-link multi-stage networks Vmlink(N1, N2, d, s), generalized folded multi-link multi-stage networks Vfold-mlink(N1, N2, d, s), generalized multi-link butterfly fat tree networks Vmlink-bft(N1, N2, d, s), and generalized hypercube networks Vhcube(N1, N2, d, s) for s=1, 2, 3 or any number in general. The embodiments of VLSI layouts are useful in wide target applications such as FPGAs, CPLDs, pSoCs, ASIC placement and route tools, networking applications, parallel & distributed computing, and reconfigurable computing.
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