Invention Grant
- Patent Title: Method of flattening a recess in a substrate and fabricating a semiconductor structure
- Patent Title (中): 使衬底中的凹部变平并制造半导体结构的方法
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Application No.: US12851561Application Date: 2010-08-06
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Publication No.: US08222163B2Publication Date: 2012-07-17
- Inventor: Chao-Wen Lay , Ching-Kai Lin
- Applicant: Chao-Wen Lay , Ching-Kai Lin
- Applicant Address: TW Kueishan, Tao-Yuan Hsien
- Assignee: Nanya Technology Corp.
- Current Assignee: Nanya Technology Corp.
- Current Assignee Address: TW Kueishan, Tao-Yuan Hsien
- Agent Winston Hsu; Scott Margo
- Main IPC: H01L21/31
- IPC: H01L21/31 ; H01L21/469

Abstract:
A recess is usually formed on the sidewall of the trench due to the dry etch. The recess may influence the profile of an element formed in the trench. Therefore, a method of flattening a recess in a substrate is provided. The method includes: first, providing a substrate having a trench therein, wherein the trench has a sidewall comprising a recessed section and an unrecessed section. Then, a recessed section oxidation rate change step is performed to change an oxidation rate of the recessed section. Later, an oxidizing process is performed to the substrate so as to form a first oxide layer on the recessed section, and a second oxide layer on the unrecessed section, wherein the second oxide layer is thicker than the first oxide layer. Finally, the first oxide layer and the second oxide layer are removed to form a flattened sidewall of the trench.
Public/Granted literature
- US20120034791A1 METHOD OF FLATTENING A RECESS IN A SUBSTRATE AND FABRICATING A SEMICONDUCTOR STRUCTURE Public/Granted day:2012-02-09
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