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US08209470B2 CPU data bus PLD/FPGA interface using dual port RAM structure built in PLD 失效
CPU数据总线PLD / FPGA接口使用双端口RAM结构内置PLD

CPU data bus PLD/FPGA interface using dual port RAM structure built in PLD
摘要：
A programmable logic device may include first and second ports in data communication with a memory block including a pair of address areas. A system using the programmable logic device may include the programmable logic device in data communication with a central processing unit and a controller. A method of using the programmable logic device may include generating a command from the central processing unit based on data read from one of the address areas and written to the second address area wherein the address areas are associated with a common memory address.
摘要（中）：

可编程逻辑器件可以包括与包括一对地址区域的存储器块进行数据通信的第一和第二端口。 使用可编程逻辑器件的系统可以包括与中央处理单元和控制器进行数据通信的可编程逻辑器件。 使用可编程逻辑器件的方法可以包括基于从一个地址区域读取的数据产生来自中央处理单元的命令并将其写入第二地址区域，其中地址区域与公共存储器地址相关联。

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