发明授权
US08188895B2 Digital signal coding method and apparatus, digital signal decoding apparatus, digital signal arithmetic coding method and digital signal arithmetic decoding method
有权
数字信号编码方法和装置，数字信号解码装置，数字信号算术编码方法和数字信号算术解码方法
- 专利标题： Digital signal coding method and apparatus, digital signal decoding apparatus, digital signal arithmetic coding method and digital signal arithmetic decoding method
- 专利标题（中）： 数字信号编码方法和装置，数字信号解码装置，数字信号算术编码方法和数字信号算术解码方法
-
申请号： US12987637申请日： 2011-01-10
-
公开(公告)号： US08188895B2公开(公告)日： 2012-05-29
- 发明人: Shunichi Sekiguchi , Yoshihisa Yamada , Kohtaro Asai
- 申请人： Shunichi Sekiguchi , Yoshihisa Yamada , Kohtaro Asai
- 申请人地址： JP Tokyo
- 专利权人： Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人： Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址： JP Tokyo
- 代理机构： Birch, Stewart, Kolasch & Birch, LLP
- 优先权： JP2002-124114 20020425
- 主分类号： H03M7/00
- IPC分类号： H03M7/00
摘要：
In a bit stream syntax containing compressed video slice data for compressed video data of a slice structure, a slice header for compressed video slice data has attached thereto a slice start code, a register reset flag indicating whether a register value, which designates a status of a codeword occurring in an arithmetic coding process, should be reset in the next transmission unit, an initial register value which indicates a register value to be used to start arithmetic coding/decoding to build/decompose the next transmission unit, only when the register reset flag indicates that the register should not be reset.
公开/授权文献
信息查询
