发明授权
- 专利标题: Reference voltage circuit
- 专利标题(中): 参考电压电路
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申请号: US12888799申请日: 2010-09-23
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公开(公告)号: US08174309B2公开(公告)日: 2012-05-08
- 发明人: Hideo Yoshino , Takashi Imura
- 申请人: Hideo Yoshino , Takashi Imura
- 申请人地址: JP Chiba
- 专利权人: Seiko Instruments Inc.
- 当前专利权人: Seiko Instruments Inc.
- 当前专利权人地址: JP Chiba
- 代理机构: Brinks Hofer Gilson & Lione
- 优先权: JP2009-221235 20090925; JP2010-180567 20100811
- 主分类号: G05F1/10
- IPC分类号: G05F1/10
摘要:
Provided is a reference voltage circuit in which a temperature characteristic of a reference voltage is excellent and a circuit scale is small. In the reference voltage circuit, for example, a temperature correction circuit separated from the reference voltage circuit is not used and a difference voltage between threshold voltages of two E-type NMOS transistors (14 and 15) is added to a threshold voltage of a D-type NMOS transistor to generate a reference voltage (Vref). Therefore, the influence of the D-type NMOS transistor on the reference voltage (Vref), which is a degradation factor of the temperature characteristic of the reference voltage (Vref), may be reduced to suppress a change in tilt and curve of the reference voltage (Vref) with respect to a temperature.
公开/授权文献
- US20110074496A1 REFERENCE VOLTAGE CIRCUIT 公开/授权日:2011-03-31
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