发明授权
US08171326B2 L1 flush mechanism to flush cache for power down and handle coherence during flush and/or after power down
有权
L1冲洗机构刷新缓存以断电并处理冲水和/或断电后的一致性
- 专利标题： L1 flush mechanism to flush cache for power down and handle coherence during flush and/or after power down
- 专利标题（中）： L1冲洗机构刷新缓存以断电并处理冲水和/或断电后的一致性
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申请号： US12785842申请日： 2010-05-24
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公开(公告)号： US08171326B2公开(公告)日： 2012-05-01
- 发明人: James B. Keller , Tse-Yu Yeh , Ramesh Gunna , Brian J. Campbell
- 申请人： James B. Keller , Tse-Yu Yeh , Ramesh Gunna , Brian J. Campbell
- 申请人地址： US CA Cupertino
- 专利权人： Apple Inc.
- 当前专利权人： Apple Inc.
- 当前专利权人地址： US CA Cupertino
- 代理机构： Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- 代理商 Lawrence J. Merkel
- 主分类号： G06F1/32
- IPC分类号： G06F1/32
摘要：
In one embodiment, a processor comprises a data cache configured to store a plurality of cache blocks and a control unit coupled to the data cache. The control unit is configured to flush the plurality of cache blocks from the data cache responsive to an indication that the processor is to transition to a low power state in which one or more clocks for the processor are inhibited.
公开/授权文献
- US20100235670A1 Fast L1 Flush Mechanism 公开/授权日：2010-09-16
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