A 3D graphics architecture in which a buffer is placed between the sequencer and the processing element (PE) array. The sequencer and PE array are not designed to run in lock step: instead the sequencer and PE array are decoupled to allow the PEs to run at 100% efficiency even when the sequencer is switching between threads and performing other flow control operations. Thus, the rate of instruction processing in the PE array is not coupled to the rate of instruction processing in the sequencer.