发明授权
- 专利标题: Selection circuit and packet processing apparatus
- 专利标题(中): 选择电路和包处理装置
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申请号: US12507872申请日: 2009-07-23
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公开(公告)号: US08032677B2公开(公告)日: 2011-10-04
- 发明人: Takeshi Sumou , Katsumi Imamura , Hideyo Fukunaga
- 申请人: Takeshi Sumou , Katsumi Imamura , Hideyo Fukunaga
- 申请人地址: JP Kawasaki
- 专利权人: Fujitsu Limited
- 当前专利权人: Fujitsu Limited
- 当前专利权人地址: JP Kawasaki
- 代理机构: Murphy & King, P.C.
- 优先权: JP2008-255315 20080930
- 主分类号: G06F13/26
- IPC分类号: G06F13/26
摘要:
An aspect of the embodiment utilizes a selection circuit that includes a first storage circuit for storing information of m×n bits each corresponding to a choice. The storage circuit indicates whether the corresponding choice is in a selectable state or not. A first round robin circuit for executing a round robin process on the second storage circuit selects one of the bits contained in the corresponding bit string and indicates that a choice is in a selectable state. A second round robin circuit executes the round robin process on the bit string having the m-bit width to select one of the bits indicating that the corresponding choice, and a control circuit controls the first and the second round robin circuit.
公开/授权文献
- US20100082864A1 SELECTION CIRCUIT AND PACKET PROCESSING APPARATUS 公开/授权日:2010-04-01
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