Invention Grant
- Patent Title: Method of fabricating semiconductor device
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Application No.: US12399140Application Date: 2009-03-06
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Publication No.: US07994039B2Publication Date: 2011-08-09
- Inventor: Shinichi Hirasawa , Shinya Watanabe
- Applicant: Shinichi Hirasawa , Shinya Watanabe
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2008-125006 20080512; JP2008-294773 20081118
- Main IPC: H01L21/28
- IPC: H01L21/28

Abstract:
A method of fabricating a semiconductor device according to one embodiment includes: forming a plurality of Si-based pattern portions above a semiconductor substrate, the plurality of Si-based pattern portions being adjacent in a direction substantially parallel to a surface of the semiconductor substrate via insulating films; forming a metal film above the plurality of Si-based pattern portions and the insulating films so as to contact with the plurality of Si-based pattern portions; processing whole areas or upper portions of the plurality of Si-based pattern portions into a plurality of silicide layers by a silicidation reaction between the plurality of Si-based pattern portions and the metal film by heat treatment; and removing the plurality of silicide layers formed above the insulating films by applying planarizing treatment to the plurality of silicide layers.
Public/Granted literature
- US20090280583A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE Public/Granted day:2009-11-12
Information query
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