发明授权
US07987345B2 Performance monitors in a multithreaded processor architecture 有权
多线程处理器架构中的性能监视器

Performance monitors in a multithreaded processor architecture
摘要:
A system comprising a plurality of execution units configured to execute, at least in part, a plurality of instruction threads; a plurality of performance monitors, each performance monitor being configured to collect performance information related to the execution of at least one instruction thread; a selected thread identifier configured to provide, during operation, the selection of at least one instruction thread; and a performance manager configured to filter, utilizing the selected thread, the information collected by the plurality of performance monitors.
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