发明授权
US07977977B1 Dynamic logic circuit with device to prevent contention between pull-up and pull-down device
有权
具有设备的动态逻辑电路,以防止上拉和下拉器件之间的争用
- 专利标题: Dynamic logic circuit with device to prevent contention between pull-up and pull-down device
- 专利标题(中): 具有设备的动态逻辑电路,以防止上拉和下拉器件之间的争用
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申请号: US12717322申请日: 2010-03-04
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公开(公告)号: US07977977B1公开(公告)日: 2011-07-12
- 发明人: Karthik Natarajan , Giridhar Narayanaswami , Spencer M. Gold , Stephen Kosonocky , Ravi Jotwani , Michael Braganza
- 申请人: Karthik Natarajan , Giridhar Narayanaswami , Spencer M. Gold , Stephen Kosonocky , Ravi Jotwani , Michael Braganza
- 申请人地址: US CA Sunnyvale
- 专利权人: Advanced Micro Devices, Inc.
- 当前专利权人: Advanced Micro Devices, Inc.
- 当前专利权人地址: US CA Sunnyvale
- 代理机构: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- 代理商 Erik A. Heter
- 主分类号: H03K19/96
- IPC分类号: H03K19/96
摘要:
A circuit including is disclosed. The circuit includes a precharge circuit configured to pull a dynamic node toward a voltage present on the voltage supply node during a precharge phase, and an evaluation circuit configured to, during an evaluation phase, pull the dynamic node toward a ground voltage responsive to a first input condition and configured to inhibit pulling of the dynamic node down responsive to a second input condition. A pull-up circuit coupled between the first dynamic node and the voltage supply node includes first and second pull-up transistors. The first pull-up transistor is configured to activate responsive to the precharge phase. The second pull-up transistor is configured to activate at a delay time subsequent to entry of the evaluation phase. When the first and second pull-up transistors are active, a pull-up path is provided between the dynamic node and the voltage supply node.
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