发明授权
US07975195B1 Scan architecture for full custom blocks with improved scan latch
有权
扫描结构,完整的自定义块与改进的扫描锁存
- 专利标题: Scan architecture for full custom blocks with improved scan latch
- 专利标题(中): 扫描结构,完整的自定义块与改进的扫描锁存
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申请号: US12547727申请日: 2009-08-26
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公开(公告)号: US07975195B1公开(公告)日: 2011-07-05
- 发明人: Kiran Joshi , Manish Shrivastava
- 申请人: Kiran Joshi , Manish Shrivastava
- 申请人地址: BM Hamilton
- 专利权人: Marvell International Ltd.
- 当前专利权人: Marvell International Ltd.
- 当前专利权人地址: BM Hamilton
- 主分类号: G01R31/28
- IPC分类号: G01R31/28
摘要:
A non-fighting fully clocked scan latch is described that is dynamically configurable to support both logic data latching and scan data latching. The described scan latch circuit design reduces a load placed on a logic data latch portion of the described circuit by a scan latch portion of the described circuit, and thereby increases the speed of the described scan latch to that of an output latch without scan capability. Power required to drive the described scan latch is reduced by clocking the circuit to avoid fighting and by reducing the number of transistors included in transistor stacks internal to the scan latch. By reducing drive power requirements, eliminating internal latch fighting, and increasing latch response, a versatile scan latch is achieved that may be successfully implemented in a wide range of circuits despite the use of different supply drive voltage, threshold voltage, source-to-drain voltage, and transistor technology combinations.
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