发明授权
- 专利标题: Managing cache coherency in a data processing apparatus
- 专利标题(中): 在数据处理设备中管理高速缓存一致性
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申请号: US11709279申请日: 2007-02-22
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公开(公告)号: US07937535B2公开(公告)日: 2011-05-03
- 发明人: Emre Özer , Stuart David Biles , Simon Andrew Ford
- 申请人: Emre Özer , Stuart David Biles , Simon Andrew Ford
- 申请人地址: GB Cambridge
- 专利权人: ARM Limited
- 当前专利权人: ARM Limited
- 当前专利权人地址: GB Cambridge
- 代理机构: Nixon & Vanderhye P.C.
- 主分类号: G06F12/00
- IPC分类号: G06F12/00 ; G06F13/00 ; G06F13/28
摘要:
Each of plural processing units has a cache, and each cache has indication circuitry containing segment filtering data. The indication circuitry responds to an address specified by an access request from an associated processing unit to reference the segment filtering data to indicate whether the data is either definitely not stored or is potentially stored in that segment. Cache coherency circuitry ensures that data accessed by each processing unit is up-to-date and has snoop indication circuitry whose content is derived from the already-provided segment filtering data. For certain access requests, the cache coherency circuitry initiates a coherency operation during which the snoop indication circuitry determines whether any of the caches requires a snoop operation. For each cache that does, the cache coherency circuitry issues a notification to that cache identifying the snoop operation to be performed.
公开/授权文献
- US20080209133A1 Managing cache coherency in a data processing apparatus 公开/授权日:2008-08-28
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