发明授权
US07925853B2 Method and apparatus for controlling memory array gating when a processor executes a low confidence branch instruction in an information handling system
有权
当处理器在信息处理系统中执行低置信度分支指令时,用于控制存储器阵列门控的方法和装置
- 专利标题: Method and apparatus for controlling memory array gating when a processor executes a low confidence branch instruction in an information handling system
- 专利标题(中): 当处理器在信息处理系统中执行低置信度分支指令时,用于控制存储器阵列门控的方法和装置
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申请号: US11969344申请日: 2008-01-04
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公开(公告)号: US07925853B2公开(公告)日: 2011-04-12
- 发明人: Michael Karl Gschwind , Robert Alan Philhower , Raymond Cheung Yeung
- 申请人: Michael Karl Gschwind , Robert Alan Philhower , Raymond Cheung Yeung
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理商 Matt Talpis; Mark P Kahler
- 主分类号: G06F12/00
- IPC分类号: G06F12/00 ; G06F13/00 ; G06F13/28
摘要:
An information handling system includes a processor with an array power management controller. The array power management controller gates off a memory array, such as a cache, to conserve power whenever a group of instructions in a branch instruction queue together as a group exhibits a confidence in the accuracy of branch predictions of branch instructions therein that is less than a first predetermined threshold confidence threshold. In one embodiment of the information handling system, the array power management controller speculatively inhibits the gating off of the memory array when confidence in the accuracy of a branch prediction for a particular currently issued branch instruction exhibits less than a second predetermined threshold confidence threshold. In this manner, the array power management controller again allows access to the memory array in the event a branch redirect is likely.
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