发明授权
- 专利标题: Clock generator, multimodulus frequency divider and deta-sigma modulater thereof
- 专利标题(中): 时钟发生器,多模式分频器及其调制器
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申请号: US12391263申请日: 2009-02-24
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公开(公告)号: US07924965B2公开(公告)日: 2011-04-12
- 发明人: Wei-Sheng Tseng , Hong-Yi Huang , Kuo-Hsing Cheng , Yuan-Hua Chu
- 申请人: Wei-Sheng Tseng , Hong-Yi Huang , Kuo-Hsing Cheng , Yuan-Hua Chu
- 申请人地址: TW Hsinchu
- 专利权人: Industrial Technology Research Institute
- 当前专利权人: Industrial Technology Research Institute
- 当前专利权人地址: TW Hsinchu
- 代理机构: Jianq Chyun IP Office
- 优先权: TW97151134A 20081226
- 主分类号: H03K21/00
- IPC分类号: H03K21/00
摘要:
A clock generator is illustrated. The clock generator mentioned above includes a multimodulus frequency divider and a delta-sigma modulator. The multimodulus frequency divider is archived by switching the phase thereof. The multimodulus frequency divider increases the operating frequency of the clock generator effectively, and has a characteristic with half period resolution for reducing the jitter of an output clock signal when its spectrum is spread. Besides, the delta-sigma modulator increases the accuracy of the triangle modulation and reduces error of quantization by adding a few components therein. Thus, the clock generator could be expanded to a programmable clock generator.
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