发明授权
US07923340B2 Method to reduce collector resistance of a bipolar transistor and integration into a standard CMOS flow
有权
降低双极晶体管的集电极电阻并集成到标准CMOS流中的方法
- 专利标题： Method to reduce collector resistance of a bipolar transistor and integration into a standard CMOS flow
- 专利标题（中）： 降低双极晶体管的集电极电阻并集成到标准CMOS流中的方法
-
申请号： US12523368申请日： 2007-02-14
-
公开(公告)号： US07923340B2公开(公告)日： 2011-04-12
- 发明人: Alan S. Chen , Mark Dyson , Nace M. Rossi , Ranbir Singh , Xiaojun Yuan
- 申请人： Alan S. Chen , Mark Dyson , Nace M. Rossi , Ranbir Singh , Xiaojun Yuan
- 申请人地址： US PA Allentown
- 专利权人： Agere Systems Inc.
- 当前专利权人： Agere Systems Inc.
- 当前专利权人地址： US PA Allentown
- 国际申请： PCT/US2007/062100 WO 20070214
- 国际公布： WO2008/100312 WO 20080821
- 主分类号： H01L21/331
- IPC分类号： H01L21/331 ; H01L21/8222
摘要：
The invention, in one aspect, provides a method for fabricating a semiconductor device. In one aspect, the method provides for a dual implantation of a tub of a bipolar transistor. The tub in bipolar region is implanted by implanting the tub through separate implant masks that are also used to implant tubs associated with MOS fabricate different voltage devices in a non-bipolar region during the fabrication of MOS transistors.
公开/授权文献
信息查询
IPC分类:
