发明授权
US07921386B2 Fabrication method for semiconductor device, exposure method, pattern correction method and semiconductor device
失效
半导体器件的制造方法,曝光方法,图案校正方法和半导体器件
- 专利标题: Fabrication method for semiconductor device, exposure method, pattern correction method and semiconductor device
- 专利标题(中): 半导体器件的制造方法,曝光方法,图案校正方法和半导体器件
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申请号: US12108660申请日: 2008-04-24
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公开(公告)号: US07921386B2公开(公告)日: 2011-04-05
- 发明人: Toshiyuki Ishimaru
- 申请人: Toshiyuki Ishimaru
- 申请人地址: JP Tokyo
- 专利权人: Sony Corporation
- 当前专利权人: Sony Corporation
- 当前专利权人地址: JP Tokyo
- 代理机构: SNR Denton US LLP
- 优先权: JP2007-117847 20070427
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
Disclosed herein is a fabrication method for a semiconductor device, including a lithography step of connecting a plurality of mask patterns to each other to form a pattern image of an area greater than the size of the mask patterns. The lithography step includes the steps of: assuring an overlapping exposure region to be exposed in an overlapping relationship by both of two mask patterns to be connected to each other, carrying out exposure transfer of the pattern portions of the two mask patterns to the overlapping exposure region to form a first measurement mark and a second measurement mark in the overlapping exposure region, and carrying out positional displacement measurement of pattern connection by the two mask patterns based on a manner of combination of main marks and sub marks of the measurement marks formed in the overlapping exposure region.
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