Herein described are at least a system and a method of reducing or decreasing the rate of interrupts transmitted by a device to a microprocessor. In a representative embodiment, the device comprises a universal asynchronous receiver/transmitter. In a representative embodiment, the rate of interrupts is reduced by receiving and using a first signal as an input to a first counter. The first counter outputs a first count, and compares the first count to a value provided by a memory. Subsequently, a second signal is generated to initiate an interrupt when the first count equals the value. In a representative embodiment, a system for delaying transmission of an interrupt from a universal asynchronous receiver/transmitter (UART) to a microprocessor comprises a counter capable of generating a count, a memory capable of storing a value, and a comparator used for comparing the count to the value.