发明授权
- 专利标题: CPU datapipe architecture with crosspoint switch
- 专利标题(中): 具有交叉点开关的CPU数据通道架构
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申请号: US11322487申请日: 2005-12-30
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公开(公告)号: US07899857B2公开(公告)日: 2011-03-01
- 发明人: Jerry W. Yancey
- 申请人: Jerry W. Yancey
- 申请人地址: US NY New York
- 专利权人: L3 Communications Corporation
- 当前专利权人: L3 Communications Corporation
- 当前专利权人地址: US NY New York
- 代理机构: Lathrop & Gage LLP
- 主分类号: G06F7/38
- IPC分类号: G06F7/38
摘要:
Provided is a programmable matrix element or “PME” (which may be part of an ASIC central processing unit) operable to manipulate a data set of real and complex numbers derived from an input signal. Specific operations may include: addition, subtraction, multiplication, accumulation, storage and scaling. Each PME includes a plurality of multi-stage signal processing modules, which may be two-staged modules. Each state, in turn, includes: at least one data manipulation module for manipulating the input signal; a crosspoint switch for facilitating the receipt and parallel distribution of an input signal/manipulated output signal; and a programmable control module operable to support data manipulation by controlling manipulation functions, storing data and routing signals. A given crosspoint switch may be programmed to interconnect data manipulation modules in “datapipe” fashion, which is to say via a specified number of parallel data pathways.
公开/授权文献
- US20070198810A1 CPU datapipe architecture with crosspoint switch 公开/授权日:2007-08-23
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