发明授权
- 专利标题: Power consumption reduction in a multiprocessor system
- 专利标题(中): 多处理器系统中的功耗降低
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申请号: US11525306申请日: 2006-09-22
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公开(公告)号: US07882379B2公开(公告)日: 2011-02-01
- 发明人: Tomochika Kanakogi
- 申请人: Tomochika Kanakogi
- 申请人地址: JP Tokyo
- 专利权人: Sony Computer Entertainment Inc.
- 当前专利权人: Sony Computer Entertainment Inc.
- 当前专利权人地址: JP Tokyo
- 代理机构: Gibson & Dernier LLP
- 代理商 Matthew B. Dernier, Esq.
- 主分类号: G06F1/32
- IPC分类号: G06F1/32
摘要:
Methods and apparatus provide for reducing power consumption by decreasing operating frequencies of waiting processors in a multiprocessor system. Power consumption may be reduced by having a processor enter a low frequency mode when the processor is in a loop waiting for data that have been locked by another processor. The frequency of operation of the waiting processor may be reduced to a fraction (one half, one quarter, etc.) of the normal, initial clock frequency. The multiprocessor system may monitor a number of times (loop count) that a waiting processor takes the wait loop and compare the number to a threshold. When the loop count is greater than or equal to the threshold, the clock frequency of the waiting processor is reduced. When the waiting processor ceases to wait and does not take the wait loop branch (e.g., because the other processor has released the lock on the data), the loop count is reset to zero and the frequency of operation of waiting processor is increased to an increased frequency, such as the normal, initial level.
公开/授权文献
- US20080077815A1 Power consumption reduction in a multiprocessor system 公开/授权日:2008-03-27
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