An analog to digital converter is provided. The converter comprises a dither gain generator, a first stage, an adder, a second stage, and a digital error correction logic. The dither gain generator generates a dither gain. The first stage receives a first voltage to generate a first digital code and a second voltage. The adder is coupled to the first stage and adds the dither voltage to the second voltage to generate a third voltage. The second stage receives the third voltage to generate a second digital code. The digital error correction logic receives and corrects the first digital code and the second digital code to generate a digital code corresponding to the first voltage.