发明授权
- 专利标题： Method and semiconductor structure for monitoring etch characteristics during fabrication of vias of interconnect structures
- 专利标题（中）： 用于在制造互连结构通孔期间监测蚀刻特性的方法和半导体结构
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申请号： US11875535申请日： 2007-10-19
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公开(公告)号： US07829889B2公开(公告)日： 2010-11-09
- 发明人: Matthias Lehr
- 申请人： Matthias Lehr
- 申请人地址： US TX Austin
- 专利权人： Advanced Micro Devices, Inc.
- 当前专利权人： Advanced Micro Devices, Inc.
- 当前专利权人地址： US TX Austin
- 代理机构： Williams, Morgan & Amerson
- 优先权： DE102007015506 20070330
- 主分类号： H01L23/58
- IPC分类号： H01L23/58
摘要：
By forming a trench-like test opening above a respective test metal region during the etch process for forming via openings in a dielectric layer stack of sophisticated metallization structures of semiconductor devices, the difference in etch rate in the respective openings may be used for generating a corresponding variation of electrical characteristics of the test metal region. Consequently, by means of the electrical characteristics, respective variations of the etch process may be identified.
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