The first control transistor is connected between a first input node for receiving a first input signal swinging between a first voltage and a second voltage and an intermediate node for outputting an output signal, and receives the second voltage at its gate. The second control transistor is connected between a second input node for receiving a second input signal swinging between a third voltage and a fourth voltage in synchronization with the first input signal and the intermediate node, and receives the third voltage at its gate. The voltage difference between the first voltage and the third voltage is smaller than or equal to the source-drain breakdown voltage of the second control transistor, and the voltage difference between the second voltage and the fourth voltage is smaller than or equal to the source-drain breakdown voltage of the first control transistor.