发明授权
- 专利标题: Open-drain output circuit
- 专利标题(中): 开漏输出电路
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申请号: US11710941申请日: 2007-02-27
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公开(公告)号: US07692451B2公开(公告)日: 2010-04-06
- 发明人: Toru Ishikawa
- 申请人: Toru Ishikawa
- 申请人地址: JP Tokyo
- 专利权人: Elpida Memory, Inc.
- 当前专利权人: Elpida Memory, Inc.
- 当前专利权人地址: JP Tokyo
- 代理机构: Foley & Lardner LLP
- 优先权: JP2006-054707 20060301
- 主分类号: H03K19/094
- IPC分类号: H03K19/094
摘要:
A pulse generation section generates a pulse which is at H-level for the predetermined period of time from the timing of the input signal DATA changing to L-level. A main output section outputs a signal of L-level with transistors P1, N1, and N2 turned ON, while the pulse generation section outputs a pulse. When the pulse falls, the transistors P1 and N1 are turned OFF, and a potential of an output node is held at L-level by resistors of a L-level holding section.
公开/授权文献
- US20070205806A1 Open-drain output circuit 公开/授权日:2007-09-06
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